Keysight Debuts HMC Compliance Test

TORONTO—With standards and specifications well-established for Hybrid Memory Cube (HMC), testing tools are arriving to keep up with product development.

Keysight Technologies recently announced what it said was the industry's first compliance test software application for HMC device and system testing. Supporting the technology's 2.1 specification, the Keysight N8839A HMC test application automates the execution of transmitter physical-layer tests on the company's Infiniium V-Series and Z-Series oscilloscopes to help memory design engineers accelerate turn-on and debug of HMC systems.

The new testing application covers electrical, timing and jitter tests, and automatically configures the oscilloscope for each test. It also generates an HTML report at the end of the test, which compares the results with the specified test limit and indicates how closely the device passes or fails each test. Engineers can easily debug signal integrity issues using the N8839A software in conjunction with the switch matrix option to connect to multiple data lanes at the same time.

In a telephone interview with EE Times, Ailee Grumbine, memory product manager for communications measurement solutions at Keysight, said as DRAM manufacturers begin to ramp up development based on HMC's most recent specification, they are looking to test before going into mass production. “That's what really motivated us."

 

 Keysight's N8839A HMC test application automates the execution of transmitter physical-layer tests on its Infiniium V-Series and Z-Series oscilloscopes.

Keysight's N8839A HMC test application automates the execution of transmitter physical-layer tests on its Infiniium V-Series and Z-Series oscilloscopes.

Grumbine said HMC said while the technology is relatively new and more expensive, there are early adopters who are looking to take advantage of the DRAM memory architecture, which is designed to support higher speeds for computer and network systems, such as 100G and 400G infrastructures. There were enough customers out there to warrant a compliance test application, she said. “We want to be early to the game."

Because the specification for HMC is published and established, Grumbine said it was fairly straightforward to develop a compliance test application. “We've already done a lot of compliance tests for similar technology." It took about three months to develop the testing software and get it to market, she said.

One challenge for testing HMC devices is that unlike testing DDR, it's currently not feasible to use interposers between the board and the DRAM. “Probing is the most challenging part," said Grumbine. “Anything we put between the board and the device breaks the board." Keysight is working with DRAM manufacturers to address this, she added.

While last year was very much about testing DDR4 and LPDDR4as adoption saw an uptick, it looks like both HMC and High Bandwidth Memory (HBM) are seeing more interest in the market. Keysight does not have a compliance test option for the latter, as yet, although the company is looking at it. In general, Grumbine said the company looks to make the testing of memory devices as quick and simple as possible so vendors can get products to market quickly and don't require staff with special skills to conduct testing.

HMC is considered to be one the potential heirs to DDR4, as is HBM, but given that it's early in the lifecycle for DDR4, all three technologies will be co-existing for the foreseeable future. The HMC specification was first released in May 2013 with version 2.0 published just over a year ago. HMC uses a vertical conduit called through-silicon via (TSV) that electrically connects a stack of individual chips to combine high-performance logic with DRAM die. The memory modules are structured like a cube, instead of being placed flat on a motherboard. It was initially announced by Micron in 2011; the majority of vendors releasing products that use HMC are part of the HMC Consortium, which was founded in October of the same year.

HBM, meanwhile, is a high-performance RAM interface for 3D-stacked DRAM memory from AMD and SK Hynix for use in conjunction with high-performance graphics accelerators and network devices.

 

—Gary Hilson is a general contributing editor with a focus on memory and flash technologies for EE Times.